LOT 2 CIRCUITS INTEGRES – CD4066BCN – Quad SPST Nrm-Opn (Logic Level 0) Ana SW

Description

CD4066BCN x 2

Quad SPST Nrm-Opn (Logic Level 0) Ana SW

TOSHIBA

Sw. Volt P-P Max.(V)=15
Analog Sw. Cur. P-P Max.=20m
r(DS)on (Ohms)=250
@I(S) (test) (A)=10k
@Vd (test) (V)=15
t(on) Max. (s) Turn-On Time=60n
Control Logic Level Low (V)=1.8
Control Logic Level High (V)=4.2
Features=Norm-Open
P(D) Max.(W) Power Dissipation=500m
Vsup(-) Nom.(V) Neg.Sup.Volt.=7.0*
Vsup(+) Nom.(V) Pos.Sup.Volt.=7.0*
Package=DIP
Pins=14
Military=N
Technology=CMOS